台湾 的 HCLTech 职位

· 컴청 · * Chipset,주데,찾준디준직를로대인. · * MCU · ...

Onsite MediaTek Hsinchu office · Sr. Digital IC Designer · ( · Sr. STA/Timing signoff CAD Engineer · ) · Responsibilities · CPU/GPU STA, high-speed & low-voltage timing signoff/timing closure · methodology process design · STA Process · development & optimization · High-speed/low ...

Onsite Meta · Xinyi · Office · Embedded Software Engineer · [Embedded Software Engineer - BSP/Kernel | Reality Labs] · This is the · VROS BSP Scale team · focusing on super scale · VR headset · and · OEM headsets · development. One current product we're supporting from · low leve ...

Onsite Google · Banqiao · or · Xindian · office. · Algorithm Developer · [ · Computer Vision and Machine Learning Engineer · ] · Responsibilities: · Design and implement · algorithms · of · detecting defects · during · manufacturing. · Integrate · and · optimize · these algorithm ...

We are seeking a highly skilled DFT/DFM Engineer to join SoC chip design team. · We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. · Throughout your time with us we offer transparent communication with seni ...

Design digital ICs for MediaTek Hsinchu office.CPU/GPU STA and timing signoff CAD engineer responsibilities. · STA process development and optimization. · ...

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV (design verification) has become an inevitable part of design group in chip development flow. · Pre-silicon Validation & Testing · Chip/SoC Design Verification & Testing · ...

Onsite Google Banqiao or Xindian office. · Algorithm Developer · [Computer Vision and Machine Learning Engineer] · Responsibilities: · Design and implement algorithms of detecting defects during manufacturing. · Integrate and optimize these algorithms within systems. · Evaluate ...

We are seeking a Digital IC Designer to join our team in Hsinchu. As a member of our design group, you will be responsible for designing digital integrated circuits using advanced technologies and tools. · CPU/GPU STA, high-speed & low-voltage timing signoff/timing closure method ...

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV (design verification) has become an inevitable part of design group in chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line ...

Onsite MediaTek Hsinchu office · Sr. Digital IC Designer. · CPU/GPU STA high-speed low-voltage timing signoff/timing closure methodology process design. · ...

Technical Manager · (Sr. Semiconductor Technical Consultant) · Qualifications · B.S. or above in Electrical/Computer Engineering or relevant work exp. · 10+ years exp. in the Digital or Analog IC design exp. & production process, w/ IC Design House exp. is preferred. · With the c ...

We are seeking a highly skilled DFT/DFM Engineer to join SoC chip design team. The successful candidate will be responsible for · DFT · and · DFM methodologies, · design, and implementation for our advanced System-on-Chip (SoC) designs. · We want you to be happy and satisfied wi ...

Onsite MediaTek Hsinchu office Application-Specific Integrated Circuit Designer STA/Timing signoff CAD Engineer Responsibilities CPU/GPU STA high-speed & low-voltage timing signoff/timing closure methodology process design. · ...